1. Field of the Invention
The present invention relates to a semiconductor display device. More specifically, it relates to a semiconductor display device which performs image display by driving pixel TFTs arranged in a matrix state, and to a semiconductor display device driving circuit. In addition, it relates to electronic equipment using such semiconductor display devices.
2. Description of the Related Art
Recently there has been rapid development in techniques of manufacturing semiconductor display devices, for example a thin film transistor (TFT), formed from semiconductor thin films on an inexpensive glass substrate. The reason for this is because the demand for active matrix type liquid crystal display devices has risen.
A TFT is placed in each of the several hundreds of thousands to several millions of pixel regions arranged in a matrix state on an active matrix type liquid crystal display device. The electric charge entering and exiting every pixel electrode is controlled by the switching function of the TFT arranged in the pixel regions.
The structure of a conventional active matrix type liquid crystal display device is shown in FIG. 18. A source signal line side driving circuit 1801 and a gate signal line side driving circuit 1802 are, normally, generically referred to as driving circuits. In recent years the driving circuit has been formed in unity with the pixel region, which is comprised of the pixel region, on the same substrate.
Further, source signal lines 1803 connected to the source signal line side driving circuit 1801, and gate signal lines 1804 connected to the gate signal line side driving circuit 1802, intersect in a pixel region 1808. Pixel thin film transistors (pixel TFTs) 1805, liquid crystal cells 1806, which sandwich liquid crystals between a pixel electrode and an opposing electrode, and storage capacitors 1807 are formed in the regions surrounded by the source signal lines 1803 and the gate signal lines 1804.
An image signal input to the source signal lines 1803 is selected by the pixel TFTs 1805 and written to a predetermined pixel electrode.
Sampling is performed on the image signal in accordance with a timing signal output from the source signal line side driving circuit 1801, and the image signal is supplied to the source signal lines 1803.
The pixel TFTs 1805 operate in accordance with a selection signal input from the gate signal line side driving circuit 1802, via the gate signal lines 1804.
[Prior Art A]
A block diagram of an example of the conventional source signal line side driving circuit 1801 is shown in FIG. 19A.
An input signal input from external to the source signal line side driving circuit, a clock signal CLK (for example, 3 V), in this case, is input to the source signal line side driving circuit. The voltage amplitude level of the input clock signal is raised by a level shifter circuit (for example, from 3 to 16 V).
In the present specification the voltage amplitude level refers to the absolute value of the difference between the highest electric potential and the lowest electric potential of a signal. If the voltage amplitude level becomes higher (goes up), this means that the electric potential difference has become larger, and if the voltage amplitude level becomes lower, this means that the electric potential difference has become smaller.
Then the increased voltage amplitude level clock signal is input to the shift register circuit. The shift register circuit operates in accordance with the input clock signal, and a start pulse signal input at the same time to the shift register circuit, and creates a timing signal in order to sample the image signal. The timing signal is input to a sampling circuit, and the sampling circuit performs sampling of the image signal based on the input timing signal.
FIG. 21 shows an example of the specific circuit structure of FIG. 19A. A level shifter circuit 11, a shift register circuit 12, a sampling circuit 13, and an image signal line 14 are arranged as shown in the diagram.
A clock signal CLK and an inverted clock signal CLKb are input to the level shifter circuit 11, and a start pulse signal SP and a drive direction switching signal SL/R are input to the shift register circuit 12 from the wirings shown in the drawing.
The clock signal CLK (for example, 3 V) is input to the level shifter circuit 11 from external to the source signal line side driving circuit. It is necessary for the voltage amplitude level of the clock signal to be of a voltage amplitude level at which the level shifter circuit 11 can operate.
Further, unwanted radiation due to the clock signal is a problem of the set. Unwanted radiation is caused by generation of high frequency components of digital circuits which use rectangular wave trains starting up very sharply. Unwanted radiation becomes larger as the signal frequency gets higher, but it can be suppressed to a certain extent by reducing the voltage amplitude level of the signal.
It is necessary to suppress the unwanted radiation to within the range conforming to the standard established by CISPR (the International Special Committee on Radio Interference). Furthermore, in addition to CISPR, it is necessary that the range conform to the standards established by other foreign and domestic organizations such as the United States FCC (Federal Communications Commission), VCCI (Voluntary Control Council for Interference by data processing equipment and electronic office machines), and the German VDE (Verband Deutscher Elektrotechniker e.v). For example, the standard established by the FCCI states that, for industrial equipment, the permitted value of unwanted radiation is 1000 xcexcV when the frequency is from 0.45 to 1.6 MHz, and is 3000 xcexcV when the frequency is from 1.6 to 30 MHz. It is necessary to reduce the voltage amplitude level of the clock signal input from external to the source signal line side driving circuit to a level in which the unwanted radiation will conform to the standards established by the CISPR and other foreign and domestic standards and cause no trouble.
The voltage amplitude level of the clock signal input to the level shifter circuit increases. An equivalent circuit diagram of the level shifter circuit 11 is shown in FIG. 20. The reference Vin denotes an input signal, and Vinb denotes an input of an inverted Vin. In addition, Vddh denotes the application of a positive voltage, and Vss denotes the application of a negative voltage. The level shifter circuit 11 is designed so that the signal input from Vin, made into a high voltage signal, and inverted, is then output from Voutb. In short, if Hi is input to Vin, then a signal corresponding to Vss is output from Voutb, and if Lo is input to Vin, then a signal corresponding to Vddh is output from Vout.
The voltage amplitude level of the clock signal is increased, by a level shifter like that shown in FIG. 20, to a voltage amplitude level that includes a certain fixed margin voltage in addition to a voltage amplitude level at which the liquid crystal is driven to a saturation state (liquid crystal saturation voltage). Further, saturation voltage indicates the liquid crystal saturation voltage in the present specification. A liquid crystal being driven into a saturation state indicates a state (saturation state) in which a change in the electro-optical characteristics following change in the liquid crystal arrangement will not accompany a further increase of the applied voltage.
The timing signal is a signal used in order to sample the image signal input to the sampling circuit. The voltage of the timing signal input to the sampling circuit is then applied to a gate electrode of a TFT which structures the analog switch of the sampling circuit. This forms a channel in the TFT which structures the analog switch, and a current flows from the source to the drain. Thus the image signal is sampled, and this is supplied to the source of the pixel TFT through the source signal line.
For example, for the case of a 5 V drive TN (twisted nematic) liquid crystal, 5 V is the saturation voltage. An alternating current drives the liquid crystal, the result being that xe2x88x925 V to +5 V, namely a 10 V voltage amplitude level, is applied to the liquid crystal. When the liquid crystal is driven in the saturation state, it is necessary to sample a 10 V image signal (in this case the image signal and the saturation voltage are equal) and supply that to the source of the pixel TFT.
In order to sample this image signal, it is necessary to apply a timing signal, with a voltage amplitude level that includes a certain fixed margin voltage (for example, +3 V) in addition to the saturation voltage, to the gate of the TFT that structures the analog switch. In short, to sample an image signal voltage of xe2x88x925 to +5 V, namely a 10 V voltage amplitude level image signal, it is necessary that the voltage amplitude level of the timing signal have the absolute value of xe2x88x928 to 8 V, in other words a voltage amplitude level of 16 V.
The margin voltage is a voltage in order to reliably supply a saturation voltage image signal to the pixel TFT source. There is a problem in that the n-channel-type TFT which constitutes the analog switch does not operate with a xc2x15 V voltage amplitude level image signal and sampling does not occur, when sampling is attempted using a timing signal with the same xc2x15 V voltage amplitude level, which does not include a margin. This is because the voltage amplitude level (5 V) of the image signal applied to the source of the n-channel TFT that constitutes the analog switch, and the voltage amplitude level (5 V) of the timing signal applied to the gate electrode, have a voltage amplitude level difference of 0 V, and the n-channel type TFT does not operate. Further, a p-channel type TFT does not operate for the same reason. Due to this, it is necessary to have the timing signal include a margin voltage in order to drive the liquid crystal to the saturation state. It is necessary that the size of the margin voltage be large enough to sample the saturation voltage image signal in accordance with the timing signal, and to reliably supply the source signal line with the signal.
Additionally, in recent years the development of large screen, high definition liquid crystal display devices has been advancing. When considering display at the same frame rate, the more the number of pixels in a liquid crystal display device increases, the higher the speed at which it is necessary to operate the shift register circuit. There is a demand for a higher frequency drive of the shift register.
The operating speed of the shift register circuit is proportional to the mobility of the shift register circuit TFT, and to the voltage amplitude level of the clock signal applied to the source, and is inversely proportional to the square of the channel length. The reason that the operating speed of the shift register circuit is inversely proportional to the square of the channel length is that if the TFT channel length is short, the resistance becomes small, and the gate capacitance becomes small.
In order to operate the shift register circuit at higher speed, it is necessary to either make the shift register circuit power supply voltage large, or to shorten the channel length, because there is a limit to the extent of the TFT mobility.
However, if power supply voltage for the shift register circuit is made higher, and the channel length is made shorter, the TFT is easily damaged by punch through and hot electrons caused by the short channel effect. Therefore it is necessary to lower the shift register circuit power supply voltage to a level that does not cause damage to the TFT.
In addition, if the voltage amplitude level of the clock signal applied to the source is reduced to a level that will not damage the TFT due to punch through or hot electrons caused by a short channel effect of the shift register circuit TFT, and if the TFT channel length is made shorter, then the TFT can not be manufactured due to limits in the design of TFTs with short channels. For that reason, the shift resister circuit can not operate at a speed higher than a certain speed. Therefore, in order to operate the shift register circuit at higher speed, it is necessary to increase the channel length to a range in which it can be made, and to increase the clock signal voltage amplitude level applied to the source to a level at which the TFT, with a channel length which can be manufactured, will operate.
In short, in order to operate the shift register circuit at higher speed, it is necessary to reduce the shift register circuit power supply voltage to a level at which the shift register circuit TFT is not damaged due to punch through or hot electrons by short channel effect, and it is necessary to increase the shift register circuit power supply voltage to a level at which the manufacturable channel length TFT will operate.
In the conventional circuit structure of FIG. 21, the clock signals (CLK, CLKb) input to the shift register circuit TFT become the same voltage amplitude level as the timing signal input to the sampling circuit because there is no level shifter circuit in between the shift register circuit and the sampling circuit. In other words, the voltage amplitude level of the clock signals input to the shift register circuit cannot be reduced to a level at which damage due to punch through or hot electrons due to the short channel effect will not occur in the TFT that constitutes the shift register circuit. Therefore the shift register circuit TFT is easily damaged.
There is a solution path for the above problems by using a liquid crystal display device structured with a LCD material that can be driven with a relatively low voltage, smaller than 3 V. However, the reliability is low because the liquid crystal used has a voltage holding rate that is low, current leaks due to the voltage applied to the liquid crystals, and the liquid crystals easily deteriorate. LCD materials that can be driven with a voltage greater than 3 V have a relatively high voltage holding rate of over 95%, and the reliability of a liquid crystal display device that uses an LCD material driven with a voltage greater than 3 V is high.
[Prior Art B]
A block diagram of another example of the conventional source signal line side driving circuit 1801 is shown in FIG. 19B.
A clock signal CLK (for example, 10 V) input from external to the source signal line side driving circuit is directly input to the shift register circuit. Then the shift register circuit operates in accordance with the input clock signal and a start pulse signal input at the same time to the shift register circuit, and a timing signal is created in order to sample the image.
The created timing signal is input to the level shifter circuit, and the voltage amplitude level is increased. The timing signal with an increased voltage amplitude level is input to the sampling circuit, and the sampling circuit performs sampling of the image signal based on the input timing signal.
FIG. 22 shows an example of the specific circuit structure of FIG. 19B. A shift register circuit 21, a level shifter circuit 22, a sampling circuit 23, and an image signal line 24 are arranged as shown in the diagram.
A clock signal CLK, an inverted clock signal CLKb, a start pulse signal SP, and a drive direction switching signal SL/R are input to the shift register circuit 21 from the wirings shown in the drawing.
The clock signal CLK (for example, 10 V) is input to the level shifter circuit 21 from external to the source signal line side driving circuit. The voltage amplitude level of the input clock signal is a voltage amplitude level at which the shift register circuit 21 can operate.
The shift register circuit 21 operates in accordance with the input clock signal, and the start pulse signal input to the shift register circuit 21 at the same time, and a timing signal is created in order to sample the image. The created timing signal is input to the level shifter circuit 22.
It has already been stated that in order to drive the liquid crystal in a saturation state, it is necessary to input a timing signal which has a voltage amplitude level that includes a certain fixed margin voltage in addition to the saturation voltage, to the sampling circuit 23. Therefore, if the voltage amplitude level of the timing signal input to the sampling circuit 23 does not meet the voltage amplitude level that includes a certain fixed margin voltage in addition to the saturation voltage, it is necessary to increase the voltage amplitude level of the timing signal. The timing signal input to the level shifter circuit 22 is increased to a voltage amplitude level that includes a certain fixed margin voltage in addition to the saturation voltage (for example, 16 V), and then output. The output timing signal is then input to the sampling circuit 23.
In order to operate the shift register circuit at high-speed, it is necessary to reduce the power supply voltage of the shift register circuit to a level that does not cause damage to the TFT of the shift register circuit 21 from punch through or hot electrons due to the short channel effect. It is also necessary to increase the power supply voltage of the shift register circuit to a level at which the TFT, with a manufacturable channel length, will operate. However, with the circuit structure of Prior Art B, if the voltage amplitude level of the clock signal, input from external to the source signal line side driving circuit, is increased to a high voltage, to a voltage amplitude level at which the shift register circuit can operate at high-speed, it is difficult to suppress the voltage amplitude level of the clock signal, input from external to the source signal line side driving circuit, to a level at which unwanted radiation does not become a problem. Further, the higher the voltage amplitude level of the clock signal input from external to the source signal line side driving circuit becomes, the larger the power consumption, which is not desirable.
There is a solution path for the above problems by using a liquid crystal display device structured with a LCD material that can be driven with a relatively low voltage, smaller than 3 V. However, the reliability is low because the liquid crystal used has a voltage holding rate that is low, current leaks due to the voltage applied to the liquid crystals, and the liquid crystals easily deteriorate. LCD materials that can be driven with a voltage greater than 3 V have a relatively high voltage holding rate of over 95%, and the reliability of a liquid crystal display device that uses an LCD material driven with a voltage greater than 3 V is high.
[Prior Art C]
A block diagram of another example of the conventional source signal line side driving circuit 1801 is shown in FIG. 19C.
A clock signal CLK (for example, 9 V) from external to the source signal line side driving circuit is input to the shift register circuit. Then the shift register circuit operates in accordance with the input clock signal and a start pulse signal input at the same time to the shift register circuit, and a timing signal is created in order to sample the image. The sampling circuit operates based on the timing signal, and the image signal is sampled.
FIG. 23 shows an example of the specific circuit structure shown in the block diagram of FIG. 19C. A shift register circuit 31, a sampling circuit 32, and an image signal line 33 are arranged as shown in the diagram.
A clock signal CLK, an inverted clock signal CLKb, a start pulse signal SP, and a drive direction switching signal SL/R are input to the shift register circuit 31 from the wirings shown in the drawing.
The clock signal CLK (for example, 9 V) is input to the shift register circuit 31 from external to the source signal line side driving circuit.
The shift register circuit 31 operates in accordance with the input clock signal, and the start pulse signal input to the shift register circuit 31 at the same time, and creates in order a timing signal for sampling the image. The created timing signal is input to the sampling circuit 32.
It is self-evident that the Prior Art C possesses the drawbacks of both Prior Art A and Prior Art B. If the liquid crystals are driven in the saturation state, the TFT of the shift register circuit is easily damaged due to punch through and hot electrons resulting from the short channel effect, so there is a problem that the channel length cannot be shortened and therefore high-speed operation is not possible.
Further, with the circuit structure of Prior Art C, at the point of input from external to the source signal line side driving circuit, the voltage amplitude level of the clock signal is a voltage amplitude level that includes a certain fixed margin voltage in addition to the saturation voltage. Therefore this cannot be suppressed enough to avoid the problems of unwanted radiation and power consumption.
There is a solution path for the above problems by using a liquid crystal display device structured with a LCD material that can be driven with a relatively low voltage, smaller than 3 V. However, the reliability is low because the liquid crystal used has a voltage holding rate that is low, current leaks due to the voltage applied to the liquid crystals, and the liquid crystals easily deteriorate. LCD materials that can be driven with a voltage greater than 3 V have a relatively high voltage holding rate of over 95%, and the reliability of a liquid crystal display device that uses an LCD material driven with a s voltage greater than 3 V is high.
[Prior Art D]
A block diagram a conventional gate signal line side driving circuit is shown in FIG. 24A.
A clock signal CLK (for example, 3 V) from external to the gate signal line side driving circuit is input to the level shifter circuit. The voltage amplitude level of the clock signal must be a voltage amplitude level at which it is possible for the level shifter circuit to operate.
The voltage amplitude level of the clock signal input to the level shifter circuit is increased (for example, from 3 V to 25 V).
It is necessary the voltage amplitude level of the selection signal input to the gate signal lines be a voltage amplitude level at which it is possible to reliably drive all of the pixel TFTs connected to the selected gate signal line. The selected signal voltage is applied to the gate electrodes of the pixel TFTs connected to the gate signal line, forming channels in the pixel TFTs. Thus a current flows from the source to the drain of the pixel TFTs, and the image signal is supplied to the liquid crystals, and the liquid crystals are driven.
The gate signal line has a long wiring and the wiring resistance is high, so there is a voltage drop when the selection signal input to the gate signal line is applied to the pixel TFT farthest away. The more the voltage drops, the more the voltage applied to the pixel TFT gate electrode becomes smaller, and in the worst case a channel cannot be formed in the pixel TFT.
To supply a pixel signal to the liquid crystals by reliably driving all of the pixel TFTs, the voltage amplitude level of the selection signal input to the gate signal line must be increased to a voltage amplitude level that includes a certain fixed margin voltage in addition to the image signal voltage amplitude level. Also, it is necessary for the selection signal to have a high voltage amplitude level, to a degree which the voltage drop due to the wiring resistance of the gate wiring will not become a problem.
The margin voltage is a voltage in order that an image signal with a voltage amplitude level that is the same as the saturation voltage is reliably supplied to the pixel electrode of the liquid crystal cell. It is necessary that the margin voltage have a size such that a saturation voltage image signal will reliably be supplied to the pixel electrode.
The increased voltage amplitude level clock signal (for example, 25 V) is input to the shift register circuit. The shift register circuit operates in accordance with the input clock signal and a start pulse signal input to the shift register circuit at the same time, and a selection signal is created in order to operate the pixel TFTs. The created selection signal is input to the gate signal line, channels are formed in the pixel TFTs, and the image signal is supplied to the liquid crystals.
It is not necessary to operate the shift register circuit at as high a speed for the gate signal line side driving circuit as it is for the source signal line side driving circuit. As stated above, the TFT operation speed is inversely proportional to the square of the channel length. The TFT channel length on the shift register circuit is longer on the gate signal line side driving circuit than on the source signal line side driving circuit, which has an operating speed slower than the source signal line side driving circuit, and it is difficult for damage to occur from punch through or hot electrons due to the short channel effect.
However, in recent years the development of large screen, high definition liquid crystal display devices has been advancing, as stated above. When considering display at the same frame rate, the more the number of pixels in a liquid crystal display device increases, the higher the speed at which it is necessary to operate the shift register circuit on the gate signal line side driving circuit, as in the source signal line side driving circuit. Accordingly, there is a demand for a higher frequency drive of the shift register in the gate signal line side driving circuit.
Then the increased voltage amplitude level clock signal is input to the shift register circuit. The shift register circuit operates in accordance with the input clock signal and a start pulse signal input at the same time to the shift register circuit, and a selection signal is created in order to reliably operate the pixel TFTs. The created selection signal is input to the gate signal lines.
It is self-evident that the Prior Art D possesses the same drawbacks as Prior Art A. With Prior Art D, in order to make it possible to reliably drive all of the pixel TFTs, it is difficult to reduce the voltage amplitude level of the selection signal input to the shift register circuit to an extent at which the shift register circuit TFT will not be damaged from punch through or hot electrons due to the short channel effect.
There is a solution path for the above problems by using a liquid crystal display device structured with a LCD material that can be driven with a relatively low voltage, smaller than 3 V. However, the reliability is low because the liquid crystal used has a voltage holding rate that is low, current leaks due to the voltage applied to the liquid crystals, and the liquid crystals easily deteriorate. LCD materials that can be driven with a voltage greater than 3 V have a relatively high voltage holding rate of over 95%, and the reliability of a liquid crystal display device that uses an LCD material driven with a voltage greater than 3 V is high.
[Prior Art E]
A block diagram of another example of a conventional gate signal line side driving circuit is shown in FIG. 24B.
A clock signal CLK (for example, 10 V) input from external to the gate signal line side driving circuit is input directly to the shift register circuit. The input clock signal has a voltage amplitude level at which it is possible for the shift register circuit to operate. The shift register circuit operates in accordance with the input clock signal and a start pulse signal input to the shift register circuit at the same time, and a selection signal is created in order to operate the pixel TFTs.
The created selection signal is input to the level shifter circuit, and the voltage amplitude level thereof is increased to a voltage amplitude level at which it is possible to reliably operate all of the pixel TFTs (for example, from 10 V to 30 V). The increased voltage amplitude level selection signal is then supplied to the gate signal lines.
It is self-evident that the Prior Art E possesses the same drawbacks as Prior Art B. With Prior Art B, if the input clock signal is given a voltage amplitude level at which high-speed operation of the shift register circuit is possible, then it is difficult to reduce it to a degree at which unwanted radiation will not become a problem. In addition, as stated above, there is a problem of not being capable of suppressing the power consumption.
There is a solution path for the above problems by using a liquid crystal display device structured with a LCD material that can be driven with a relatively low voltage, smaller than 3 V. However, the reliability is low because the liquid crystal used has a voltage holding rate that is low, current leaks due to the voltage applied to the liquid crystals, and the liquid crystals easily deteriorate. LCD materials that can be driven with a voltage greater than 3 V have a relatively high voltage holding rate of over 95%, and the reliability of a liquid crystal display device that uses an LCD material driven with a voltage greater than 3 V is high.
[Prior Art F]
A block diagram of another example of a conventional gate signal line side driving circuit is shown in FIG. 24C.
A clock signal CLK (for example, 20 V) from external to the gate signal line side driving circuit is input to the shift register circuit. At this point, the voltage amplitude level of the input clock signal has the necessary selection signal voltage amplitude level to drive the liquid crystals in the saturation state.
The shift register circuit then operates in accordance with the clock signal input to the shift register circuit and a start pulse signal input to the shift register circuit at the same time, and a selection signal is created in order to operate the pixel TFTs. The created selection signal is input to the gate signal lines.
It is self-evident that the Prior Art F possesses the same drawbacks as Prior Art C. If all of the pixel TFTs are to be reliably driven, the channel length cannot be shortened because the shift register circuit TFT is easily damaged by punch through and hot electrons due to the short channel effect, and therefore there is a problem of not being cable of operating at high-speed.
There is a solution path for the above problems by using a liquid crystal display device structured with a LCD material that can be driven with a relatively low voltage, smaller than 3 V. However, the reliability is low because the liquid crystal used has a lo voltage holding rate that is low, current leaks due to the voltage applied to the liquid crystals, and the liquid crystals easily deteriorate. LCD materials that can be driven with a voltage greater than 3 V have a relatively high voltage holding rate of over 95%, and the reliability of a liquid crystal display device that uses an LCD material driven with a voltage greater than 3 V is high.
The problem points from Prior Arts A to F are brought together below. A liquid crystal display device which can be driven at a relatively low voltage below 3 V, the voltage holding rate is low, there is a current leak due to the voltage applied to the liquid crystals, and the liquid crystals easily deteriorate, so the reliability is low. Thus it is desirable to increase the liquid crystal display device reliability by using a display device with a high voltage holding rate and driven with a relatively high voltage. However, if the liquid crystals are driven to a saturation state by a conventional source signal line side driving circuit when a liquid crystal display device driven by a relatively high voltage is used, then the shift register circuit TFT is easily damaged by punch through and hot electrons due to the short channel effect. Further, the change to large scale display panels in recent years has brought with it the demand for high-speed operation of the shift register circuit. However, if the power consumption and the unwanted radiation with a conventional source signal line side driving circuit are suppressed, high-speed operation of the shift register circuit is difficult, and the demands accompanying large screens cannot be met.
Similarly for the gate signal line side driving circuit, if all of the pixel TFTs are to be reliably driven, the shift register circuit TFT is easily damaged by punch through and hot electrons due to the short channel effect. If the power consumption and the unwanted radiation are suppressed, then high-speed operation of the shift register circuit is difficult, and the demands accompanying large screens cannot be met.
There is a demand for the realization of a driving circuit that can drive without these types of problems, and for a high reliability semiconductor display device which has the driving circuit.
Thus an object of the present invention is to realize a driving circuit in which a voltage amplitude level of a clock signal input to a shift register circuit is set to obtain the voltage and channel length suitable for driving the shift register circuit at high-speed. By doing so, another object of the invention is to realize a high-speed operation driving circuit, and a semiconductor display device having the driving circuit, with which even if liquid crystals are driven in a saturation state, or even if all of the pixel TFTs are reliably operated, the shift register circuit will not be damaged. Further, another object of the invention is to make high-speed operation of the shift register circuit possible even if the voltage amplitude level of the clock signal, input from external to the driving circuit, is suppressed to a level at which power consumption and unwanted radiation do not become problems.
In the present invention, the voltage amplitude level of the clock signal input from external to the driving circuit is increased by a level shifter circuit, and the clock signal is then input to the shift register circuit. A timing signal created by the shift register circuit is additionally input to the level shifter circuit. The voltage amplitude level is increased in two stages.
As such, by arranging a level shifter circuit before and after the shift register circuit, the present invention reduces the shift register circuit power supply voltage so that the shift register circuit TFT is not damaged by punch through or hot electrons due to the short channel effect. Further, the shift register circuit is operated such that the channel length of the shift register circuit TFT is lengthened to an extent at which it can be formed, and the voltage amplitude level of the clock signal applied to the TFT source is increased to the level at which the TFT operates. Thus, even if the liquid crystals are driven in the saturation state, and even if all of the pixel TFTs are reliably operated, the shift register circuit is not damaged, a driving circuit which operates at high-speed, and a semiconductor display device which contains the driving circuit are provided. In addition, a semiconductor device having a driving circuit with which it is possible to suppress power consumption and unwanted radiation, to such an extent that they do not become problems even when the shift register circuit is operated at high speed, is provided.
The structure of the present invention is explained below.
In accordance with a preferred embodiment of the present invention, there is provided a source signal line side driving circuit having a first level shifter circuit, a second level shifter circuit, a shift register circuit, and a sampling circuit, characterized in that:
the first level shifter circuit increases the voltage of an input signal, which is input to the first level shifter circuit from external to the source signal line side driving circuit, to a voltage amplitude level at which it is possible for the shift register circuit to operate, and inputs the result to the shift resister circuit;
the shift register circuit creates a timing signal, based on the input signal input from the first level shifter circuit, in order to sample an image signal supplied from external to the source signal line side driving circuit, and inputs the created timing signal to the second level shifter circuit;
the second level shifter circuit further increases the voltage amplitude level of the input timing signal, and inputs the result to the sampling circuit; and
the sampling circuit samples the image signal in accordance with the input timing signal, and supplies the result to source signal lines connected to the source signal line side driving circuit. Thus the above objects of the present invention are achieved.
In addition, in accordance with another preferred embodiment of the present invention, there is provided a source signal line side driving circuit having a first level shifter circuit, a second level shifter circuit, a shift register circuit, and a sampling circuit, characterized in that:
the first level shifter circuit increases the voltage of a clock signal, which is input to the first level shifter circuit from external to the source signal line side driving circuit and has a voltage amplitude level at which it is possible for the first level shifter circuit to operate, to a voltage amplitude level at which it is possible for the shift register circuit to operate, and inputs the result to the shift register circuit;
the shift register circuit creates a timing signal, based on the clock signal input to the shift register circuit, in order to sample an image signal supplied from external to the source signal line side driving circuit, and inputs the created timing signal to the second level shifter circuit;
the second level shifter circuit increases the voltage amplitude level of the timing signal input to the second level shifter circuit, to a voltage amplitude level that includes a certain fixed margin voltage in addition to the saturation voltage of a liquid crystal, and inputs the result to the sampling circuit; and
the sampling circuit samples the image signal in accordance with the timing signal input to the sampling circuit, and supplies the result to source signal lines connected to the is source signal line side driving circuit. Thus the above objects of the present invention are achieved.
In addition, in accordance with another preferred embodiment of the present invention, there is provided a gate signal line side driving circuit having a first level shifter circuit, a second level shifter circuit, and a shift register circuit, characterized in that:
the first level shifter circuit increases the voltage of an input signal, which is input from external to the gate signal line side driving circuit, to a voltage amplitude level at which it is possible for the shift register circuit to operate, and inputs the result to the shift register circuit;
the shift register circuit creates a selection signal, based on the input signal which is input to the shift register circuit, and inputs the created selection signal to the second level shifter circuit; and
the second level shifter circuit increases the voltage amplitude level of the input selection signal, to a voltage amplitude level at which it is possible for all pixel TFTs connected to gate signal lines to reliably operate, and either directly, or through a buffer circuit, supplies the increased voltage selection signal to the gate signal lines. Thus the above objects of the present invention are achieved.
In addition, in accordance with another preferred embodiment of the present invention, there is provided a gate signal line side driving circuit having a first level shifter circuit, a second level shifter circuit, and a shift register circuit, characterized in that:
the first level shifter circuit increases the voltage of a clock signal, which is input to the first level shifter circuit from external to the gate signal line side driving circuit and has a voltage amplitude level at which it is possible for the first level shifter circuit to operate, to a voltage amplitude level at which it is possible for the shift register circuit to operate, and inputs the result to the shift register circuit;
the shift register circuit, based on the clock signal input to the shift register circuit, creates a selection signal which operates pixel TFTs connected to the gate signal line side driving circuit through gate signal lines, and inputs the created selection signal to the second level shifter circuit; and
the second level shifter circuit increases the voltage amplitude level of the selection signal input to the second level shifter circuit, to a voltage amplitude level at which it is possible for all of the pixel TFTs connected to the gate signal lines to reliably operate, and supplies the selection signal, which has been increased in voltage by the second level shifter circuit, to the gate signal lines. Thus the above objects of the present invention are achieved.
In addition, in accordance with another preferred embodiment of the present invention, there is provided a semiconductor display device having:
a pixel region in which a plurality of pixel TFTs are arranged in a matrix state;
a plurality of source signal lines which are connected to source electrodes of the multiple number of pixel TFTs, respectively;
a plurality of gate signal lines which are connected to gate electrodes of the plurality of pixel TFTs, respectively;
a source signal line side driving circuit connected to the plurality of source signal lines; and
a gate signal line side driving circuit connected to the plurality of gate signal lines, characterized in that:
the source signal line side driving circuit has a first level shifter circuit, a second level shifter circuit, a shift register circuit, and a sampling circuit;
the first level shifter circuit increases the voltage of a clock signal, which is input to the first level shifter circuit from external to the source signal line side driving circuit and has a voltage amplitude level at which it is possible for the first level shifter circuit to operate, to a voltage amplitude level at which it is possible for the shift register circuit to operate, and inputs the result to the shift register circuit;
the shift register circuit creates a timing signal, based on the clock signal input to the shift register circuit, in order to sample an image signal supplied from external to the source signal line side driving circuit, and inputs the created timing signal to the second level shifter circuit;
the second level shifter circuit increases the voltage amplitude level of the timing signal input to the second level shifter circuit, to a voltage amplitude level that includes a certain fixed margin voltage in addition to the saturation voltage of a liquid crystal, and inputs the result to the sampling circuit; and
the sampling circuit samples the image signal in accordance with the timing signal input to the sampling circuit, and supplies the result to the source signal lines. Thus the above objects of the present invention are achieved.
The source signal line side driving circuit may be formed with the pixel region on the same substrate.
In addition, in accordance with another preferred embodiment of the present invention, there is provided a semiconductor display device having:
a pixel region in which a plurality of pixel TFTs are arranged in a matrix state;
a plurality of source signal lines which are connected to source electrodes of the plurality of pixel TFTs, respectively;
a plurality of gate signal lines which are connected to gate electrodes of the plurality of pixel TFTs, respectively;
a source signal line side driving circuit connected to the plurality of source signal lines; and
a gate signal line side driving circuit connected to the plurality of gate signal lines, characterized in that:
the gate signal line side driving circuit has a first level shifter circuit, a second level shifter circuit, and a shift register circuit;
the first level shifter circuit increases the voltage of a clock signal, which is input to the first level shifter circuit from external to the gate signal line side driving circuit and has a voltage amplitude level at which it is possible for the first level shifter circuit to operate, to a voltage amplitude level at which it is possible for the shift register circuit to operate, and inputs the result to the shift register circuit;
the shift register circuit, based on the clock signal input to the shift register circuit, creates a selection signal which operates the pixel TFTs connected to the gate signal line side driving circuit through the gate signal lines, and inputs the created selection signal to the second level shifter circuit; and
the second level shifter circuit increases the voltage amplitude level of the selection signal input to the second level shifter circuit, to a voltage amplitude level at which it is possible for all of the pixel TFTs connected to the gate signal lines to reliably operate, and supplies the selection signal, which has been increased in voltage by the second level shifter circuit, to the gate signal lines. Thus the above objects of the present invention are achieved.
The gate signal line side driving circuit may be formed with the pixel region on the same substrate.
In addition, in accordance with another preferred embodiment of the present invention, there is provided a semiconductor display device having:
a pixel region in which a plurality of pixel TFTs are arranged in a matrix state;
a plurality of source signal lines which are connected to source electrodes of the plurality of pixel TFTs, respectively;
a plurality of gate signal lines which are connected to gate electrodes of the plurality of pixel TFTs, respectively
a source signal line side driving circuit connected to the plurality of source signal lines; and
a gate signal line side driving circuit connected to the plurality of gate signal lines, characterized in that:
the source signal line side driving circuit has a first level shifter circuit, a second level shifter circuit, a first shift register circuit, and a first sampling circuit;
the first level shifter circuit increases the voltage of a clock signal, which is input to the first level shifter circuit from external to the source signal line side driving circuit and has a voltage amplitude level at which it is possible for the first level shifter circuit to operate, to a voltage amplitude level at which it is possible for the first shift register circuit to operate, and inputs the result to the first shift register circuit;
the first shift register circuit creates a timing signal, based on the clock signal input to the first shift register circuit, in order to sample an image signal supplied from external to the source signal line side driving circuit, and inputs the created timing signal to the second level shifter circuit;
the second level shifter circuit increases the voltage amplitude level of the timing signal input to the second level shifter circuit, to a voltage amplitude level that includes a certain fixed margin voltage in addition to the saturation voltage of a liquid crystal, and inputs the result to the first sampling circuit;
the first sampling circuit samples the image signal in accordance with the timing signal input to the first sampling circuit, and supplies the result to the source signal lines;
the gate signal line side driving circuit has a third level shifter circuit, a fourth level shifter circuit, and a second shift register circuit;
the third level shifter circuit increases the voltage of a clock signal, which is input to the third level shifter circuit from external to the gate signal line side driving circuit and has a voltage amplitude level at which it is possible for the third level shifter circuit to operate, to a voltage amplitude level at which it is possible for the second shift register circuit to operate, and inputs the result to the second shift register circuit;
the second shift register circuit, based on the clock signal input to the second shift register circuit, creates a selection signal which operates the pixel TFTs connected to the gate signal line side driving circuit through the gate signal lines, and inputs the created selection signal to the fourth level shifter circuit; and
the fourth level shifter circuit increases the voltage amplitude level of the selection signal input to the fourth level shifter circuit, to a voltage amplitude level at which it is possible for all of the pixel TFTs connected to the gate signal lines to reliably operate, and supplies the selection signal, which has been increased in voltage by the fourth level shifter circuit, to the gate signal lines. Thus the above objects of the present invention are achieved.
The source signal line side driving circuit and the gate signal line side driving circuit may be formed with the pixel region on the same substrate.
In addition, in accordance with another preferred embodiment of the present invention, there is provided a driving circuit for a semiconductor display device of digital drive system, the driving circuit having a first level shifter circuit, a second level shifter circuit, a third level shifter circuit, a first latch circuit, a second latch circuit, a shift register circuit, and a D/A converter circuit, the driving circuit characterized in that:
the first level shifter circuit increases the voltage of an input signal, which is input to the first level shifter circuit from external to the driving circuit, to a voltage amplitude level at which it is possible for the shift register circuit to operate, and inputs the result to the shift register circuit;
the shift register circuit creates a timing signal, based on the input signal input from the first level shifter, which determines the timing for writing a digital signal, supplied from external to the driving circuit, to the first latch circuit, and inputs the result to the first latch circuit;
the digital signal is input to the third level shifter circuit, and a digital signal output from the third level shifter circuit is input to the first latch circuit at the timing determined by the timing signal;
the digital signal input to the first latch circuit, after logical operation, undergoes logical operation in the second latch circuit, and is output; and
the output digital signal is input to the D/A converter circuit, through the second level shifter circuit, and is converted to analog. Thus the above objects of the present invention are achieved.